1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Background Art
A power MOSFET is designed for dealing with large electric power. An example of the power MOSFET includes a trench gate type MOSFET (for example, refer to JP-A 2003-92405 (KOKAI)). Performance required for the power MOSFET changes with a circuit in which the power MOSFET is provided. For example, when using the power MOSFET as a load switch, low on-resistance performance is required in many cases so as to reduce conduction loss. On the other hand, when using the power MOSFET for high speed switching in a DC-DC converter and the like, plural performances such as low on-resistance performance, low capacitance performance, and low gate resistance performance, are required in many cases so as to improve conversion efficiency.
An LSI provided with the trench gate type MOSFET will be described. Generally, a substrate region of such LSI includes an FET section (transistor section) for controlling a current, and a gate line section for transmitting a gate signal. The FET section largely influences on on-resistance or capacitance, and the gate line section largely influences on gate resistance. With respect to such LSI, efforts to satisfy required performance have been continued by improving the on-resistance, capacitance, and gate resistance. With respect to the on-resistance, reduction of resistance of a source line has been advanced by improving assembly techniques. For example, it has become common to adopt strap structure instead of wire structure for leading a source electrode (for example, refer to JP-A 2003-332576 (KOKAI)).
Reduction of the gate resistance with reducing the on-resistance is achieved, for example, by reducing the gate resistance by certain means with reducing the source resistance by the strap structure. The reduction of the gate resistance can be achieved, for example, by forming a silicide layer on a polysilicon layer which forms the gate line, so as to reduce the resistance of the line itself. However, it is difficult to achieve, only with this method, the low resistance that satisfies enough the required performance. The reduction of the gate resistance can be also achieved, for example, by extending the width of the gate line or by increasing the number of gate lines. However, since it is necessary in this method to reduce the FET section as its trade off, it leads to an increase in the on-resistance.